1. Field of the Invention
The present invention relates to a memory testing system, and more particularly, to a memory testing system with data compressing function.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional memory module 100 being written with data compressing function. As shown in FIG. 1, the memory module 100 comprises a testing system 110 and a Dynamic Random Access Memory (DRAM) 120. The memory module 100 comprises four data ends D0, D1, D2, and D3, and an address end A. Similarly, the DRAM 120 comprises the corresponding data ends D0′, D1′, D2′, and D3′, and an address end A′. The memory module 100 is disposed for inputting addresses to the address end A for accessing data stored in the DRAM 120 through the data ends D0, D1, D2, and D3. During the testing procedure, the memory module 100 uses data compressing function for writing data into the DRAM 120. More particularly, the testing system 110 short-circuits the data ends D0′, D1′, D2′, and D3′, and inputs testing data TD to the data end D0 and inputs testing address RA to the address end A. In this way, the testing data TD can be written into the DRAM 120 through the data ends D0˜D3 to the memory cells corresponding to the data ends D0′˜D3′ and the testing address RA. Furthermore, the testing address RA can be a row address. For example, when the testing address RA is [00], it represents the word line WL0, when the testing address RA is [01], it represents the word line WL1, when the testing address RA is [10], it represents the word line WL2, and when the testing address RA is [11], it represents the word line WL3.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating a conventional memory module 100 reading data with the data compressing function. After the testing procedure with data compressing of FIG. 1 is done (the testing data is written into the corresponding memory cells), the testing system 100 reads the stored testing data with the same manner as the writing procedure with the data compression. That is, the testing system 110 input the same testing address RA to the corresponding address end A′ of the DRAM 120 through the address end A. In this way, the corresponding memory cells of the DRAM 120 output previously written testing data to the comparator CMP1 through the data ends D0′˜D3′. Thus, the comparator CMP1 compares the received data, and determines if the received data are all the same and accordingly outputs a comparing signal S1 to the data end D0. Meanwhile, the data end D0′ also outputs the stored data S2 (the previously testing data) to the data end D0. In this way, a user can determines if the memory cell corresponding to the testing address RA is failed according to the comparing signal S1, the stored data S2, and the testing data TD. More particularly, when the comparing signal S1 determines that the received data of the comparator CMP1 are not entirely the same, it means that failed memory cells exist in the memory cells corresponding to the address RA; when the comparing signal S1 determines that the received data of the comparator CMP1 are entirely the same, it can be further determined if failed memory cells exist in the memory cells corresponding to the address RA by comparing the stored data S2 and the testing data TD. In such condition, if the stored data S2 and the testing data TD are the same, it means that no failed memory cells exist in the memory cells corresponding to the address RA; if the stored data S2 is not the same as the testing data TD, it means that failed memory cells exist in the memory cells corresponding to the address RA.
Please refer to FIG. 3 and FIG. 4 together. FIG. 3 and FIG. 4 are diagrams illustrating memory cells of two different types in a DRAM. As shown in FIG. 3, the switch SW1 is controlled by the word line WL. When the word line WL controls the switch SW1 to turn on, the memory cell X1 receives data from the bit line BL through the switch SW1. When the data transmitted from the bit line BL is logic “0”, the memory cell X1 stores the data as logic “0”; on the other hand, when the data transmitted from the bit line BL is logic “1”, the memory cell X1 stores the data as logic “1”. As shown in FIG. 4, the switch SW2 is controlled by the word line WL. When the word line WL controls the switch SW2 to turn on, the memory cell X2 receives data from the bit line BLB through the switch SW2. When the data transmitted from the bit line BLB is logic “1”, the memory cell X2 stores the data as logic “0”; on the other hand, when the data transmitted from the bit line BLB is logic “0”, the memory cell X2 stores the data as logic “1”.
Please refer to FIG. 5 and FIG. 6 together. FIG. 5 and FIG. 6 are diagrams illustrating the depositions of the memory cells in DRAMs. As shown in FIG. 5 and FIG. 6, the memory cells are interwoven by the bit lines BL and BLB of the data ends D0′˜D3′ and the word lines WL0˜WL7 of the address end (the corresponding row addresses RA are [000]˜[111]). As shown in FIG. 5 (only take row addresses WL3˜WL0 for example, the rest addresses are similar), when the data stored in the all corresponding memory cells are all logic “1”, the logic “1” is written at the data ends D1′˜D3′ by the row address WL3, the logic “0” is written at the data ends D1′˜D3′ by the row address WL2, the logic “0” is written at the data ends D1′˜D3′ by the row address WL1, and the logic “1” is written at the data ends D1′˜D3′ by the row address WL0. In this way, the sixteen memory cells corresponding to the row addresses WL3˜WL0 and the data ends D1′˜D3′ all store logic “1”. As shown in FIG. 6 (only take row addresses WL3˜WL0 for example, the rest addresses are similar), when the data stored in the all corresponding memory cells are all logic “0”, the logic “0” is written at the data ends D1′˜D3′ by the row address WL3, the logic “1” is written at the data ends D0′˜D3′ by the row address WL2, the logic “1” is written at the data ends D1′˜D3′ by the row address WL1, and the logic “0” is written at the data ends D1′˜D3′ by the row address WL0. In this way, the sixteen memory cells corresponding to the row addresses WL3˜WL0 and the data ends D1′˜D3′ all store logic “0”. Only the memory cells disposed as disclosed in FIG. 5 and FIG. 6 can be testified if any failed by the data compressing manner disclosed as in FIG. 1 and FIG. 2.
Please refer to FIG. 7 and FIG. 8 together. FIG. 7 and FIG. 8 are diagrams illustrating other depositions of memory cells in DRAMs. As shown in FIG. 7 and FIG. 8, the memory cells are also interwoven by the bit lines BL and BLB of the data ends D1′˜D3′ and the word lines WL0˜WL7 of the address end (the corresponding row addresses RA are [000]˜[111]). As shown in FIG. 7 (only take row addresses WL3˜WL0 for example, the rest addresses are similar), if the logic “1” is written at the data ends D1′˜D3′ by the row address WL3, the memory cells corresponding to the data ends D0′ and D2′ store logic “1”, but the memory cells corresponding to the data ends D1′ and D3′ store logic “0”. In such condition, the memory cells corresponding to the row address WL3 cannot store same logic data by writing same logic data. As shown in FIG. 8 (only take row addresses WL3˜WL0 for example, the rest addresses are similar), if the logic “0” is written at the data ends D1′˜D3′ by the row address WL3, the memory cells corresponding to the data ends D0′ and D2′ store logic “0”, but the memory cells corresponding to the data ends D1′ and D3′ store logic “1”. In such condition, the memory cells corresponding to the row address WL3 cannot store same logic data by writing same logic data. Therefore, the memory cells disposed as disclosed in FIG. 7 and FIG. 8 cannot be testified if any failed by the data compressing manner disclosed as in FIG. 1 and FIG. 2.